The dynamic random access memory (DRAM) device represented by the diagram of FIG. 1 stores digital information or data in an arrangement of memory cells 3. An arrangement of memory cells is called an array. The cells 3 are arranged in the array in a configuration of intersecting rows 5 and columns 6. The rows 5 are also referred to as wordlines 5. Each memory cell comprises a storage capacitor (not shown) capable of holding a charge and a metal-oxide semiconductor field effect transistor (MOSFET) (not shown) for accessing the capacitor charge; hereinafter this transistor is referred to as an access transistor. The charge is a voltage potential referred to as a data bit and is typified as either a high voltage or a low voltage. Therefore, the memory has two states; often thought of as the true logic state and the complementary logic state. The data bit is amplified and latched to the digit lines 7 by sense amplifier 8.
There are two options available in a DRAM memory; a bit of data may be stored in a specific cell in the write mode, or a bit of data may be retrieved from a specific cell in the read mode. The data is either transferred from the digit lines 7 to Input/Output lines (I/O) 9 in the read mode; or transferred from the I/O lines 9 to the digit lines 7 in the write mode. In either case, the data is transferred through MOSFETs 10 used as switching devices and called decode transistors. For each bit of data stored, its true logic state is available at a first I/0 line 11 and its complementary logic state is available at a second I/O line 13, designated I/O complement. For purposes of this discussion, I/O and I/O complement lines are often referred to as just I/O lines 9. Although each cell 3 is only connected to one digit line 7 through an activated access transistor, each cell 3 is electrically referenced to two digit lines 7, referred to as a digit line pair 15, through the sense amplifiers 8. The digit line pair 15 comprises the "digit line" 17 for coupling true data and the "digit bar line" 19 for coupling complementary data. Typically, the digit line 17 is referred to as digit and the digit bar line 19 is referred to as digit bar. The digit line pair 15 couples the true and complementary data between the selected cell 3 and the I/O lines.
In order to read from or write to a cell 3, the particular cell 3 in question must be selected or sometimes referred to as "addressed." A particular cell 3 is selected when the row decoder 21 activates a wordline 5 and the column decoder 23 activates a column 6. The electrical intersection of the activated wordline 5 and activated column 6 determines which cell 3 has been selected.
A supply potential V.sub.CC and a ground reference potential are available to the circuitry of the memory device. Between cycles of cell selection it is necessary to equilibrate the digit lines of each digit line pair 15 in a memory array to the same voltage, usually V.sub.CC /2. This equilibration of the digit lines is often referred to as the precharge cycle. Equilibrate circuitry (not shown) parallel with the sense amplifier essentially shorts the digit lines together and holds them at V.sub.CC /2. This equilibration is necessary so that the digit lines 7 are ready to receive data during the next cycle.
The I/O lines also equilibrate between cycles of cell selection by circuitry configured in parallel with the I/O and I/O complement. 3/5 V.sub.CC is typically the equilibrate voltage of the I/O lines.
In order to facilitate an understanding of the present invention, pertinent aspects of a typical write operation to a single cell are explained below with reference to FIG. 2. FIG. 2 more fully depicts the circuitry relevant to two digit line pairs 15A and 15B of the digit line pairs 15 shown in FIG. 1. The numbers pertinent to components in FIG. 1 are relevant to similar components in FIG. 2.
Digits 17A and 17B are connected to memory cells 3A and 3B respectively and are accessed through row 5A. Digit bars 19A and 19B are connected to memory cells 3C and 3D respectively and are accessed through row 5B. Therefore, memory cells 3A and 3B store data in true form and memory cells 3C and 3D store data in complementary or inverse form. The p sense amplifiers 8A and 8B and the n sense amplifiers 8C and 8D latch data on the digit line pairs 15A and 15B respectively during read and write operations.
During standby switching transistors 24 comprising the pull up p-type MOSFETs (p switching transistors) 25 and the pull down n-type MOSFET (n switching transistor) 26 are off and the data remains stored in cells 3A through 3D. During a write or read operation all of the p 25 and n 26 transistors are actuated. The p switching transistors 25 are actuated by a low signal applied to their gates. Once actuated, the p switching transistors 25 couple the supply voltage V.sub.CC 27 to the circuit. The n switching transistor 24 is actuated by a high signal applied to its gate 26. Once actuated, the n switching transistor 24 couples the ground reference potential 28 to the circuit.
For example, assume cell 3A is selected for a write operation. An active output from the row decoder activates wordline 5A. The active wordline 5A actuates the cells' 3A and 3B access transistors 29A and 29B pertinent to wordline 5A, while access transistors 29C and 29D pertinent to inactive wordline 5B remain deactivated. The switching transistors 24 are actuated and digit 17A is latched to the true data stored in cell 3A while digit bar 19A is latched to the complement of the true data. Similarly, digit 17B is latched to the true data stored in cell 3B while digit bar 19B is latched to the complement of the true data. Next the column decoder activates column 6A which in turn actuates decode transistors 10A. Column 6B remains inactive since it was not activated by the column decoder. Consequently decode transistors 10B remain off. In a write mode the input data is coupled through the actuated decode transistors 10A from the I/O lines 9 to the digit line pair 15A where the input data overwrites the data previously latched to digit line pair 15A. The data on digit line pair 15B is not disturbed since decode transistors 10B are off.
FIG. 3 is a portion of a DRAM 41 having a memory 43 comprising 16 individual memory arrays similar to memory array 45. Each array comprises 256K (K=1024) memory cells. Each memory cell stores a bit of digital information. In this case, the array is capable of storing 256 kilobits (262,144 bits). For any given address location a corresponding cell on each individual array is selected. Corresponding to each array is a DQ pin (not shown) in electrical communication with its respective array for accepting the bit of digital information from sources external to the DRAM in a write operation and from the internal memory cells in a read operation. In this discussion the designation DQ refers to a DQ pin and the ensuing subscript references the array to which the DQ pin corresponds. For example, digital information written to the fourth array is available at DQ.sub.4, and digital information read from the seventh memory array is available at DQ.sub.7.
Sixteen bits of information is called a word, and a memory cell is selected in each array to comprise the word. Eight bits of information comprises a byte. Typically, memory arrays 1 through 8 and memory arrays 9 through 16 comprise a byte.
Instructions, comprising an output enable (OE) signal and a write enable (WE) signal, generated in a central processing unit (CPU) control the read and write operations of a typical DRAM. (Throughout this discussion designations OE and WE will be considered the OE and WE signals unless stated otherwise, another option being the physical OE and WE outputs.) The active and inactive logic states of the OE and WE instructions determine whether data is written to or read from a memory cell. In order to read data from a memory cell, OE needs to be in an active logic state and WE needs to be in an inactive logic state. In order to write data into a memory cell, WE needs to be in an active logic state and OE needs to be in an inactive logic state. Both the read and write operations are preceded by an active row address strobe (RAS) signal and also require an active column address strobe (CAS) signal. In typical DRAMs, the WE and the OE are not activated at the same time. This is because the data ports are shared for input and output data. The DRAM logic inhibits the condition of both the OE and WE signals active at the same time by either not allowing it or by disabling the DRAM's ability to transmit data to the output.
FIG. 4 is a timing diagram depicting the logic states of the OE and WE for typical read and write operations. Both operations require an active RAS signal 46 preceding an active CAS signal 47. OE 48 and WE 49 are active low signals, therefore when OE 48 is asserted low at point 51 the data 52 is read from the memory cell, and when WE 49 is asserted low at point 53 the data 52 is written to the memory cell.
The DRAM arrays can be thought of as being arranged in two banks. In the case of a 16 memory array device, a first or lower bank comprising memory arrays 1 through 8 and a second or upper bank comprising memory arrays 9 through 16.
The references contained herein to "upper" and "lower" "lower" data ports, and to corresponding control signals are not intended to specify physical location, but are merely a reference to separate groups of these arrays, data ports, and control signals, as is understood by those skilled in the art.
Wide word DRAMs are characterized as a DRAM device having eight or more output bits. Some wide word DRAMs have either two WE signals or two CAS signals for byte control. The first device allows writes to one bank, byte write; or writes to both banks, word writes. The latter device allows reads or writes to one bank, byte reads and byte writes respectively; or reads or writes to both banks, word reads and word writes respectively.
Micron Technology, Inc. is developing a 256K by 16 DRAM device (16 memory arrays each containing 256K memory cells) having either two WE signal inputs or two CAS signal inputs. In both cases the two inputs drive NOR NAND logic internal to the DRAM device. The two WE input device is utilized to provide a word write or byte writes. The two CAS input device is utilized to provide a word write, byte writes, a word read, or byte reads. Neither device, as currently conceived, provides a split read/write operation, an operation where the data in one bank is read while the data is being written to the remaining bank, both banks accessed by the same address.
The 1991 Micron Technology, Inc. MOS Data Book provides a complete description of the two WE (MT4C16256/8) and two CAS (MT4C16257/9) devices being developed by Micron Technology, Inc.